1. Technical Field
The present invention relates to a semiconductor device employing a trench structure as a MOS gate, and a method of fabricating such a semiconductor device. More specifically, the present invention relates to a semiconductor device provided with gate oxide film formed on the walls of trenches and having improved characteristics, and a method of fabricating such a semiconductor device.
2. Background Art
FIG. 16 is an exemplary diagram of the construction of a conventional power device employing a trench as a MOS gate, such as an IGBT (insulated-gate bipolar transistor). FIG. 16(a) is a typical view of trenches, FIG. 16(b) is a sectional view of the power device taken on line A-Axe2x80x2 aligned with the longitudinal axis of the trench in FIG. 16(a), and FIG. 16(c) is a sectional view of the power device taken on line B-Bxe2x80x2 extending across the trenches in FIG. 16(a).
Shown in FIG. 16 are an nxe2x88x92 type diffused layer 1, an n type diffused layer 2, a p+ type heavily doped diffused layer 3, a p type base layer 4, a diffused n+ type emitter layer 5, trenches 7, a gate insulating film 11, a gate 12, a silicon dioxide film 15, interlayer insulating films 16 and 17, a p+ type region 18, a silicide layer 19, a barrier metal layer 20, and an aluminum layer 20. In this conventional trenched MOS gate construction, the surface of the gate 12 lies below a plane including the surface of a silicon wafer, i.e., below a plane including the tops of the trenches.
FIG. 17 shows, for comparison, a conventional planar MOS gate, in which parts like or corresponding to those shown in FIG. 16 are designated by the same reference numerals and the description thereof will be omitted.
FIGS. 18 to 20 are exemplary diagrams of the steps of fabricating a conventional power device employing a trench as a MOS gate, such as an IGBT (insulated-gate bipolar transistor).
The method will be described. As shown in FIG. 18(a), an n type region 2 and a p+ type region 3 are formed on the lower surface of an nxe2x88x92 type region 1 of a semiconductor substrate 30, such as a silicon substrate, and a doped p type region 4 is formed on the upper surface of the nxe2x88x92 type region 1. A heavily doped n+ type region 5 is formed selectively in portions of the doped p type region 4. Trenches 7 are formed through the p type doped region 4 and the n+ type regions 5. Then, the walls and top ends of the trenches 7 are smoothed.
As shown in FIG. 18(b), a gate insulating film 11 of silicon dioxide is formed so as to cover the walls of the trenches 7 and the surface of the wafer 30. The gate insulating film 11 is a silicon dioxide film.
As shown in FIG. 18(c), a low-resistance polysilicon film for forming gate electrodes 12 is deposited over the entire surface of the wafer 30 so as to fill up the trenches 7.
Then, as shown in FIG. 18(d), the polysilicon film is patterned to form the gate electrodes 12. A silicon dioxide film 15 is formed on the gate electrodes 12 as shown in FIG. 19(a).
Then, as shown in FIG. 19(b), CVD films 16 and 17 are deposited by CVD to form an interlayer insulating film over the entire surface of the wafer 30.
Then, the oxide films 16 and 17 are etched to form trenched MOS gates as shown in FIG. 19(c).
Then, as shown in FIG. 20, a silicide layer 19, a barrier metal layer 20 and an aluminum layer 21 are formed by sputtering and lamp annealing, and an electrode 22 is formed to complete a trenched IGBT.
In the conventional device of the construction as shown in FIG. 16 thus fabricated, a projection is formed along a Si/SiO2 boundary in a region C shown in FIG. 16(b). The thickness of portions of the gate insulating film 11 in the region C and a region D is reduced, which deteriorates the characteristics and reliability of the gate insulating film 11 formed on the walls of the trenches 7.
Since the n+ type emitter layer 5 and the p type base layer 4 are exposed on the sidewalls of the trenches 7, the impurities of the diffused layers diffuse into the gate insulating film 11 when forming the gate insulating film 11 in the process of FIG. 18(b). Consequently, the characteristics and reliability of the gate insulating film 11 deteriorate.
The present invention has been made to solve those problems and it is therefore an object of the present invention to provide a semiconductor device, such as a power device employing a trench as a MOS gate, of a device construction capable of improving the characteristics of an insulating film, such as a gate oxide film, formed on the walls of the trenches, and a method of fabricating such a semiconductor device.
According to one aspect of the present invention, a trenched semiconductor device comprises a semiconductor substrate provided with at least one trench in a major surface thereof. An insulating film is formed on the wall of the trench to extend onto the major surface of the semiconductor substrate. Further, a conductive part is filled up in the trench to extend onto the insulating film on the major surface of the semiconductor substrate.
In another aspect of the present invention, the thickness of the portion of the insulating film is increased preferably at the top portion of the trench so that the thickness of the portion of the conductive part is reduced preferably at the top portion of the trench.
In another aspect of the present invention, the insulating film is continuously formed in the adjacent trenches and on the major surface of the semiconductor substrate therebetween, and the conductive part is continuously formed filling up the adjacent trenches and extending onto the insulating film on the major surface of the semiconductor substrate therebetween.
In another aspect of the present invention, a capacitor area of the portion of the insulating film, lying on the major surface of the semiconductor substrate, is 5% or above of a total capacitor area of the insulating film.
In another aspect of the present invention, a gate edge length of the portion of the insulating film, lying outside the trench, is 30% or above of a total gate edge length of the insulating film.
In another aspect of the present invention, the insulating film is composed of either a two-layer construction consisting of a thermal oxide film and a CVD film formed on the thermal oxide film, a two-layer construction consisting of a CVD film and a thermal oxide film formed on the CVD film, or a three-layer construction consisting of a thermal oxide film, a CVD film formed on the thermal oxide film, and a thermal oxide film formed on the CVD film.
In another aspect of the present invention, the conductive part contains implanted nitrogen.
In another aspect of the present invention, the semiconductor substrate is a silicon wafer, the insulating film is a silicon dioxide film, and the conductive part is made of polysilicon.
In another aspect of the present invention, the trench sidewall of the semiconductor substrate serves as a channel, the insulating film serves as a gate insulating film, and the conductive part serves as a gate.
According to another aspect of the present invention, a trenched semiconductor device comprises a semiconductor substrate provided with at least one trench in a major surface thereof. An insulating film is formed on the wall of the trench to extend onto the major surface of the semiconductor substrate. A conductive part is formed at least in the trench. Further, the thickness of the portion of the insulating film on the major surface of the semiconductor substrate is at least twice the thickness of the portion of the insulating film on the wall of the trench.
For reference, the trenched semiconductor device may be fabricated in either of the following methods.
In one fabricating method, at least one trench is formed in a major surface of a semiconductor substrate. An insulating film is formed on the wall of the trench and on the major surface of the semiconductor substrate. A conductive film is formed in the trench and over the major surface of the semiconductor substrate. A portion of the conductive film a predetermined distance apart from the trench is removed to leave a conductive film in the trench and on the insulating film surrounding the trench.
In another fabricating method, at least one trench is formed in a major surface of a semiconductor substrate. A first insulating film is formed over the wall of the trench and the major surface of the semiconductor substrate. A first conductive film is formed in the trench and on the major surface of the semiconductor substrate. A first conductive part is formed by removing the portion of the first conductive film at the upper portion of the trench and on the major surface of the semiconductor substrate. A second insulating film is formed over the entire surface of the major surface of the semiconductor substrate. At least an opening is formed through the second insulating film so as to reach the first conductive part formed in the trench, leaving the second insulating film over the first insulating film. Further, a second conductive part is formed in the opening so as to be connected to the first conductive part.
In another fabricating method, the insulating film and the conductive film are formed to extend continuously across the adjacent trenches.
In another fabricating method, an insulating film on the wall of the trench and the major surface of the semiconductor. substrate is formed so that the thickness of the portion of the insulating film, formed on the major surface of the semiconductor substrate, is not less than twice that of the portion of the insulating film formed on the wall of the trench.
Other and further objects, features and advantages of the invention will appear more fully from the following description.